Posts: 607
Threads: 553
Joined: Dec 2013
[SIZE="4"][COLOR="red"]CS302 GDB Discussion and Solution Ideas Spring Fall 2014 Due Date 13th August 2014
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The topic of Graded Discussion Board:
There are three edge-triggered flip-flops namely SR, D and J-K that are used in digital logic circuits and every flip-flop has its own operation. Which flip flop will be better in performance against each factor given below?
Power consumption
Delay (in terms of output)
Give solid arguments to validate your view.
You may give another type of Flip Flop if any, that you think is better.
A concise, coherent and to the point comment is preferred over lengthy comment having irrelevant details, unnecessary/lengthy comments will have negative impact. Your comment must not be more than 5-7 lines. Comments, posted on regular Lesson's MDB or sent through email will not be considered in any case. Any request about such an acceptance will not be catered.
Posts: 607
Threads: 553
Joined: Dec 2013
All FF are just small asynchronous state machines. At one time it was useful to think in terms of individual FF operation rather than the larger design. Especially the now extinct JK FF reflected the concepts of analog design carried over to digital systems, but analog systems are mostly single signals and not multi-bit symbols or states. The concept of "edge-triggered" is actually misleading because what actually happens is the clock or set/reset inputs can be removed after some short time when the FF feedback has arrived to maintain the new state, so what matters is not the transition but the minimum pulse width in the clock or set/reset signal. You should know what these things are and modern logic design systems usually includes the := (colon-equal) operator to signify a (~DFF) registered signal, but no significant digital design is done with discrete FF chips and gates. You need to know how to program a FPGA or other PLD but forget ~7400 chips. You will need to know how to design for PCB trace impedance and avoid reflections, but you should never need to worry about fan-in/out. This is the 21st century. Two stages of NAND or NOR gates makes an AND-OR structure from which any logic can be compiled, usually by software. If you are doing logic reduction by hand, you will make mistakes, so write your logic in high level terms that are not confused by logic inversion etc.
