11-15-2010, 07:27 PM
What will be the logic levels on the external SRC buses when each of the given SRC instruction is executing on the processor? Complete Table: A all numbers are in the decimal number system, unless noted otherwise. (Assume the required missing information if necessary). Also Specify memory addressing modes for each of the SRC instructions given in Table.SRC instruction
RTL Equivalent
Address Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r9,4(r2)
Ld r4,4
Ld r3, M[r3]
Move r3, r2
Table: A
Assumptions:
·1 All memory content is aligned properly.
·2 In other words, all the memory accesses start at addresses divisible by 4.
·3 Value in the PC = 000DC348h
Memory map with assumed values
Register map with assumed values
RTL Equivalent
Address Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r9,4(r2)
Ld r4,4
Ld r3, M[r3]
Move r3, r2
Table: A
Assumptions:
·1 All memory content is aligned properly.
·2 In other words, all the memory accesses start at addresses divisible by 4.
·3 Value in the PC = 000DC348h
Memory map with assumed values
Register map with assumed values